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The ARMv7-M architecture supports another way to disable exceptions using a register called the BASEPRI register.
ARMv7-M exceptions are prioritized; Each exception can be assigned an 8-bit priority.
If the BASEPRI register is set to a non-zero priority value, then it will filter exceptions in this sense:
Exceptions with priority lower than or equal to the BASEPRI register will be disabled;
Exceptions with priority higher than the BASEPRI register will still be enabled;
Normally this interrupt prioritization is used to support nested interrupt handling, but it can also be used for disabling of all exceptions if configured properly.

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