\[LSI\]
%DevDesc2% = SYMMPI_Inst, PCI\VEN_1000&DEV_0622
%DevDesc3% = SYMMPI_Inst, PCI\VEN_1000&DEV_0624
%DevDesc4% = SYMMPI_Inst, PCI\VEN_1000&DEV_0626
%DevDesc5% = SYMMPI_Inst, PCI\VEN_1000&DEV_0628
%DevDesc6% = SYMMPI_Inst, PCI\VEN_1000&DEV_0030
%DevDesc7% = SYMMPI_Inst, PCI\VEN_1000&DEV_0032
%DevDesc8% = SYMMPI_Inst, PCI\VEN_1000&DEV_0050
%DevDesc9% = SYMMPI_Inst, PCI\VEN_1000&DEV_0054
%DevDesc10% = SYMMPI_Inst, PCI\VEN_1000&DEV_0058
%DevDesc11% = SYMMPI_Inst, PCI\VEN_1000&DEV_0056
%DevDesc12% = SYMMPI_Inst, PCI\VEN_1000&DEV_0640
%DevDesc13% = SYMMPI_Inst, PCI\VEN_1000&DEV_0646
%DevDesc14% = SYMMPI_Inst, PCI\VEN_1000&DEV_0062
\[DELL\]
%DevDescD1% = SYMMPI_Inst, PCI\VEN_1000&DEV_0054&SUBSYS_1F041028
%DevDescD2% = SYMMPI_Inst, PCI\VEN_1000&DEV_0054&SUBSYS_1F051028
%DevDescD3% = SYMMPI_Inst, PCI\VEN_1000&DEV_0054&SUBSYS_1F061028
%DevDescD4% = SYMMPI_Inst, PCI\VEN_1000&DEV_0054&SUBSYS_1F071028
%DevDescD5% = SYMMPI_Inst, PCI\VEN_1000&DEV_0054&SUBSYS_1F081028
%DevDescD6% = SYMMPI_Inst, PCI\VEN_1000&DEV_0054&SUBSYS_1F091028
%DevDescD7% = SYMMPI_Inst, PCI\VEN_1000&DEV_0058&SUBSYS_1F0E1028
%DevDescD8% = SYMMPI_Inst, PCI\VEN_1000&DEV_0058&SUBSYS_1F0F1028
%DevDescD9% = SYMMPI_Inst, PCI\VEN_1000&DEV_0058&SUBSYS_1F101028 |